feat: add model comparisons and sanitize session files
- Rename gamma to glm5 and model to minimax-m2.7 - Add model_comparison/ directory with head-to-head analyses - Sanitize all session.jsonl files: remove absolute paths and usernames - Remove __pycache__ artifacts - Add .gitignore
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# Fused Softmax + Top-K: Design Document
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## 1. Problem Statement
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Given logits `[B, T, V]` (e.g., batch=64, seq_len=128, vocab=50257), produce:
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- **indices** `[B, T, K]` — the K highest-probability token indices per row
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- **probs** `[B, T, K]` — their softmax probabilities
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**Constraint:** Never write the full V-length softmax vector to global memory.
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---
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## 2. Algorithm: Online Softmax + Register Min-Heap
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### 2.1 Core Idea
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We fuse three operations — **softmax computation**, **top-K selection**, and **probability rescaling** — into a single pass over the logits. This is an instance of the *online softmax* algorithm (Milakov & Gimelshein, 2018) extended with a streaming top-K heap.
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### 2.2 Online Softmax Recurrence
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Standard softmax requires two passes: one for the max, one for the sum-of-exps. The online variant maintains running statistics:
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```
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m_j = max(x_0, ..., x_j) // running maximum
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d_j = Σ_{i≤j} exp(x_i - m_j) // running sum, always relative to current max
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```
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Update rule for each new element `x_j`:
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```
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m_{j} = max(m_{j-1}, x_j)
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d_{j} = d_{j-1} * exp(m_{j-1} - m_{j}) + exp(x_j - m_{j})
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```
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This is **numerically stable** — all exponentials use `x - m_j` where `m_j` is the running max, so no term exceeds `exp(0) = 1`.
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### 2.3 Streaming Top-K Heap
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Simultaneously, each thread maintains a sorted array of size K in registers:
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```
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insert(value, index):
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if value <= heap[0]: // heap[0] = K-th largest seen so far
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return // reject — not in top-K
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find position via linear scan (K ≤ 32, so ~5 compares average)
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shift lower elements down
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place new element
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```
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For K ≤ 32 this register-resident sorted array outperforms a binary heap because:
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- No indirection / pointer chasing
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- The GPU's branch predictor handles the predictable comparison pattern well
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- Register access is ~0 latency vs. shared memory's ~20 cycle latency
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---
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## 3. Kernel Architecture
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### 3.1 Mapping: One Warp per Row
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```
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Grid: ceil(B*T / WARPS_PER_BLOCK) blocks
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Block: WARPS_PER_BLOCK × WARP_SIZE threads (default: 8 × 32 = 256)
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Warp: one (b,t) row
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```
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Each warp cooperatively processes one row of length V. Lane `j` (0..31) processes elements at indices `j, j+32, j+64, ...`.
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### 3.2 Three-Phase Pipeline
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```
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┌─────────────────────────────────────────────────────────────────┐
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│ Phase 1: Local Pass (per-warp, parallel across lanes) │
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│ │
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│ Each lane reads V/32 logits in a coalesced strided pattern │
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│ Each lane maintains: │
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│ • local_max, local_sum (online softmax statistics) │
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│ • TopKHeap<K> (K best logits seen by this lane) │
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│ │
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│ Warp reduce → warp_max, warp_sum │
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├─────────────────────────────────────────────────────────────────┤
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│ Phase 2: Cross-Warp Merge (shared memory) │
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│ │
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│ Only needed when WARPS_PER_BLOCK > 1 (i.e., multiple warps │
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│ process different rows — they still need to sync for shared │
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│ memory reuse). Within a single warp, Phase 2 is trivial. │
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│ │
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│ • Warp 0 reduces global max/sum from all warps │
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│ • Each warp writes its local top-K heap to shared memory │
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│ • Warp 0 merges WARPS_PER_BLOCK heaps → global top-K │
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│ • Rescale: prob_i = exp(val_i - global_max) / global_sum │
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├─────────────────────────────────────────────────────────────────┤
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│ Phase 3: Write Output │
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│ │
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│ Lane 0 of warp 0 writes K (prob, index) pairs to global mem │
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└─────────────────────────────────────────────────────────────────┘
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```
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### 3.3 Data Flow Diagram
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```
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Global Memory (logits [B,T,V])
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│
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▼ coalesced reads, V/32 per lane
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┌───────────────┐
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│ Registers │ Lane 0 Lane 1 ... Lane 31
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│ │ [heap] [heap] [heap]
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│ │ [lmax] [lmax] [lmax]
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│ │ [lsum] [lsum] [lsum]
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└──────┬────────┘
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│ warp shuffle (reduce_max, reduce_sum)
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▼
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┌───────────────┐
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│ Warp-level │ warp_max, warp_sum (broadcast)
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│ consensus │ merged heap via shared memory
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└──────┬────────┘
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│
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▼
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Global Memory (probs [B,T,K], indices [B,T,K])
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```
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---
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## 4. Memory Access Pattern
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### 4.1 Global Memory Reads (Logits)
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**Pattern: Strided coalesced access**
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```
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Warp for row r reads logits[r*V + 0], logits[r*V + 1], ..., logits[r*V + V-1]
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Lane 0: reads indices 0, 32, 64, 96, ...
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Lane 1: reads indices 1, 33, 65, 97, ...
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...
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Lane 31: reads indices 31, 63, 95, 127, ...
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```
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Consecutive lanes read consecutive addresses → **perfectly coalesced** 128-byte transactions. Each 128-byte cache line is fully utilized by 32 `float` values.
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**Memory efficiency:** V reads per row, 100% coalesced. No redundant loads.
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### 4.2 Global Memory Writes (Output)
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Each row writes exactly `2K` values (K probabilities + K indices). For K=10, that's 80 bytes — negligible compared to reading V×4 bytes (200KB for V=50k).
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**Writes are coalesced within a warp** because consecutive warps write consecutive rows, and lane 0 handles the output for its row.
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### 4.3 Shared Memory
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Used for cross-warp heap merge. Total footprint per block:
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```
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float warp_max[8] = 32 bytes
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float warp_sum[8] = 32 bytes
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float heap_buf[8][32] = 1024 bytes
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int idx_buf[8][32] = 1024 bytes
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─────────
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Total ≈ 2 KB
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```
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Well within the 48KB shared memory limit. **No bank conflicts** because each warp writes to a different row of `heap_buf[warp_id][...]`, and during the merge phase only warp 0 reads (sequentially, from its own perspective).
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### 4.4 Register Usage
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Per thread:
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- Online softmax state: 2 floats (8 bytes)
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- TopKHeap<K=10>: 10 floats + 10 ints (80 bytes)
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- Loop variables: ~4 floats (16 bytes)
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- **Total: ~104 bytes/thread**
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For a 256-thread block: ~26 KB of register file usage. Comfortably fits modern GPU register files (64KB–256KB per SM).
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---
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## 5. Warp-Level Optimization Strategy
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### 5.1 Shuffle-Based Reductions
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The max and sum reductions use `__shfl_xor_sync` (butterfly pattern):
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```
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Step 1: exchange with lane ^ 16 → 16 pairs
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Step 2: exchange with lane ^ 8 → 8 quads
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Step 3: exchange with lane ^ 4 → 4 groups of 8
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Step 4: exchange with lane ^ 2 → 2 groups of 16
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Step 5: exchange with lane ^ 1 → 1 group of 32
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```
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5 steps × 2 ops (max + sum) = **10 shuffle instructions total**. No shared memory, no synchronization needed within a warp.
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### 5.2 Why Not One Warp Per Row with Vector Loads?
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Alternative: use a wider type (`float4`) to read 4 values per lane, reducing the loop iterations by 4×. This is beneficial when V is very large:
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```
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// Vectorized load variant (Phase 1 inner loop)
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float4 vec = reinterpret_cast<const float4*>(logits_row)[v];
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float x0 = vec.x, x1 = vec.y, x2 = vec.z, x3 = vec.w;
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// Process 4 elements per iteration
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```
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**Trade-off:** Increases register pressure (4× more values live at once) but reduces loop overhead and improves memory throughput via wider transactions. Recommended when V > 10K.
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### 5.3 Occupancy Considerations
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| Parameter | Value |
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|--------------------|---------|
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| Threads/block | 256 |
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| Registers/thread | ~26 |
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| Shared memory/block| ~2 KB |
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| Blocks/SM (A100) | 16–20 |
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| Rows in flight/SM | 128–160 |
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The kernel is **not register-heavy** and uses minimal shared memory, allowing high occupancy and effective latency hiding.
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---
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## 6. Complexity Analysis
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### 6.1 Per-Row Work
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| Operation | Reads | Writes | Compute |
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|--------------------------|----------|---------|-------------------|
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| Read logits | V | 0 | 0 |
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| Online max/sum | 0* | 0 | V × (1 max + 1 exp + 2 FMAs) |
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| Top-K heap insert | 0* | 0 | V × ~5 compares + ~2.5 moves avg |
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| Warp reduce | 0 | 0 | 10 shuffles |
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| Final rescale (K values) | 0* | 2K | K × (1 exp + 1 mul) |
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| **Total** | **V** | **2K** | **~6V + 10 + 2K FLOPs** |
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*All intermediate values are in registers.
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### 6.2 Bandwidth vs Compute Bound Analysis
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For V = 50,257 and K = 10:
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**Memory traffic per row:**
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```
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Reads: V × 4 bytes = 201 KB
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Writes: K × 8 bytes = 80 bytes
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Total: ~201 KB
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```
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**Compute per row:**
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```
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~6 × 50,257 = 301,542 FLOPs (approximate)
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```
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**Arithmetic intensity:**
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```
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AI = 301,542 FLOPs / 201,028 bytes ≈ 1.5 FLOP/byte
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```
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**NVIDIA A100 specs:**
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```
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Peak bandwidth: 2039 GB/s → compute/bw ratio = 19.5 TFLOPS / 2039 GB/s ≈ 9.6 FLOP/byte
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Peak FP32: 19.5 TFLOPS
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```
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**Conclusion: AI (1.5) << ratio (9.6) → kernel is BANDWIDTH BOUND.**
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This means:
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1. **The bottleneck is reading V logits from global memory**, not compute.
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2. Optimizations should focus on memory access patterns (coalescing, caching) not arithmetic.
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3. The fusion saves one full write+read of the `[B,T,V]` tensor (~201 KB/row), directly translating to ~2× end-to-end speedup vs. separate softmax + top-K.
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### 6.3 Comparison to Naive Implementation
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```
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Naive (separate kernels):
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Kernel 1: softmax
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Read V logits → Write V probabilities (201 KB + 201 KB = 402 KB I/O)
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Kernel 2: top-k
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Read V probabilities → Write K results (201 KB + 80 bytes = 201 KB I/O)
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Total I/O: ~603 KB/row
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Kernel launch overhead: 2×
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Fused (this kernel):
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Read V logits → Write K results (201 KB + 80 bytes = 201 KB I/O)
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Total I/O: ~201 KB/row
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Kernel launch overhead: 1×
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Savings:
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Memory I/O: 3× reduction (603 KB → 201 KB per row)
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Kernel launches: 2× reduction
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Effective speedup: ~2.5–3× (bandwidth-bound, so I/O directly maps to time)
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```
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For a real workload (B=64, T=128, V=50257):
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```
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Naive: 64 × 128 × 603 KB = 4.7 GB global memory traffic
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Fused: 64 × 128 × 201 KB = 1.6 GB global memory traffic
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Savings: 3.1 GB avoided
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At A100 bandwidth (2039 GB/s):
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Naive time: ~2.3 ms
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Fused time: ~0.8 ms
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Speedup: 2.9×
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```
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---
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## 7. Advanced Optimizations
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### 7.1 FP16 Input with FP32 Accumulation
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For mixed-precision workloads (logits stored as `__half`):
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```cuda
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// Read 2 values per load, accumulate in FP32
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__half2 h2 = reinterpret_cast<const __half2*>(logits_row)[v];
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float x0 = __half2float(h2.x);
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float x1 = __half2float(h2.y);
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```
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This halves memory traffic (V × 2 bytes instead of V × 4 bytes), doubling throughput for bandwidth-bound workloads.
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### 7.2 Multi-Row Per Warp (for Small V)
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When V < 1024, each warp has spare bandwidth. Assign multiple rows per warp:
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```
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for (int row_offset = 0; row_offset < ROWS_PER_WARP; row_offset++) {
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int row = base_row + row_offset;
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// ... process row ...
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}
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```
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This amortizes warp-management overhead and improves occupancy for small-V cases.
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### 7.3 Async Copy (Hopper/Ada Lovelace)
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```cuda
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// Pipeline loads with cp.async to overlap compute and memory
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cp.async.ca.shared.global [smem_ptr], [gmem_ptr], 16;
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```
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Overlaps the next chunk's load with the current chunk's heap insertions. Beneficial when V > 10K and the compute path has enough latency to hide.
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### 7.4 Warp-Level Heap Merge for Large WARPS_PER_BLOCK
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When using many warps per block, the serial merge by warp 0 becomes a bottleneck. Alternative:
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```
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1. Each warp writes its K values to shared memory
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2. Tournament merge using warp shuffles:
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- Round 1: warp 0 vs warp 1, warp 2 vs warp 3, ...
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- Round 2: winners merge
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- Final: one warp produces global top-K
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3. Each round uses warp-cooperative merge of two sorted arrays
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```
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This reduces merge complexity from O(WARPS × K) to O(K × log(WARPS)).
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---
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## 8. Correctness: Numerical Stability
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The algorithm maintains numerical stability through three mechanisms:
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1. **Subtract running max before exp:** All calls to `expf()` use `x - current_max`, ensuring the argument is ≤ 0. No overflow possible.
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2. **Rescaling on max update:** When `current_max` increases, we multiply the running sum by `exp(old_max - new_max)`, which is in (0, 1]. No overflow; minimal underflow risk.
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3. **Final rescaling:** `prob_i = exp(val_i - global_max) / global_sum`. Since `global_sum ≥ 1.0` (it includes `exp(global_max - global_max) = 1.0`), division is safe.
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**Comparison with log-sum-exp:**
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The online algorithm computes exactly `Σ exp(x_i - max(x))` which is equivalent to `exp(logsumexp(x) - max(x))`. The final probabilities are identical to standard numerically-stable softmax to within floating-point rounding.
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---
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## 9. Summary Table
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| Metric | Naive (separate) | Fused (this work) | Improvement |
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|---------------------------|--------------------|---------------------|----------------|
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| Global memory reads | 2V per row | V per row | 2× |
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| Global memory writes | V + 2K per row | 2K per row | ~V/(2K)× |
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| Total I/O per row | ~3V | ~V | 3× |
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| Kernel launches | 2 | 1 | 2× |
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| Intermediate tensor | V floats/row | 0 (registers) | ∞ |
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| Numerically stable | Yes | Yes | — |
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| Register pressure | Low | Moderate (~26 regs) | Acceptable |
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| Shared memory | None | ~2 KB | Minimal |
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| Bandwidth utilization | Wastes BW on intermediate | Optimal | — |
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| Effective speedup | Baseline | **2.5–3×** | — |
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