sleepy
6ad84d543c
3-model council (GLM-5.1, Minimax-M2.7, Kimi k2p5) analyzed Intel Arc GPU performance issues and produced patches for llama.cpp: Phase 1 - SYCL Sync: Enable graph execution by default (GGML_SYCL_DISABLE_GRAPH) Phase 2 - SYCL Kernel: Fix VER_GEN12/13 thresholds, tune DMMV_X/MMV_Y Phase 3 - Vulkan Intel: Arc 140T device-ID Xe2 override Includes: - Phased apply script (apply-phase.sh [1|2|3|all]) - Master apply script with --status/--reverse/--dry-run - Per-phase READMEs with testing checklists - Council deliberation logs (gitignored in logs/) Verified: all patches apply/reverse cleanly via git apply. Static verification: VER_GEN arithmetic and DMMV_X divisibility pass.
38 lines
1.3 KiB
Markdown
38 lines
1.3 KiB
Markdown
# Phase 2 — SYCL Kernel Tuning
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**Depends on:** Phase 1 (should be applied and tested first)
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## 0001-fix-ver-gen-thresholds.patch
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Fixes VER_GEN12 (1,000,000 → 1,200) and VER_GEN13 (1,001,030 → 1,300).
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The original VER_GEN12 value was an unreachable placeholder that caused all Intel
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Arc GPUs (cc≈1255 for A770) to fall through to the NVIDIA Ampere tuning path in
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all MMQ kernels. After this patch, Intel discrete GPUs use the VER_GEN12 path.
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## 0002-tune-dmmv-xy-for-arc.patch
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Changes presets.hpp: DMMV_X 32→64, MMV_Y 1→2.
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Doubles the data processed per thread in DMMV kernels and doubles rows per
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work-group. All common model widths (4096-14336) are divisible by 64.
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## 0003-tune-dmmv-xy-common-hpp.patch
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Same changes as 0002 but in common.hpp (duplicate definitions).
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### Expected impact
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5-15% additional improvement on top of Phase 1.
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### ⚠️ Needs Benchmarking
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DMMV_X=64 and MMV_Y=2 were chosen analytically, not empirically. If MMV_Y=2
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causes register spills (check with `GGML_SYCL_DEBUG=1`), revert 0002+0003 and
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try DMMV_X=64 with MMV_Y=1 only.
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### Testing checklist
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- [ ] Build succeeds
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- [ ] Unit tests pass
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- [ ] Dense model inference produces correct output
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- [ ] No assertion failures (`ncols % GGML_SYCL_DMMV_X == 0`)
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- [ ] Benchmark comparison vs Phase 1 only
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